1. Field of the Invention
The present invention relates to techniques for reducing voltage noise in electrical circuits. More specifically, the present invention relates to a method and an apparatus for providing capacitive decoupling at the wafer level to reduce voltage noise on an integrated (IC) circuit device, such as a microprocessor chip.
2. Related Art
As microprocessors become progressively faster, voltage noise in the microprocessor core is becoming a significant factor in limiting system performance. Higher operating frequencies are causing circuitry within the microprocessor core to switch at faster rates. This faster switching can result in significant “step currents,” which are caused for example by changing code patterns, sleep cycles, etc. Step currents can cause a significant voltage drop on the microprocessor die which is proportionate to L(di/dt), where L is the loop inductance from core power to core ground as seen from the microprocessor die, where di is the step current, and where dt is the time frame over which the step current occurs. If this voltage drop (or any other form of voltage noise) causes the voltage at the microprocessor core to drop below a minimum voltage, Vmin, an error in the circuitry can potentially arise. Hence, the voltage drop at the microprocessor core caused by step currents can limit the maximum operating frequency, Fmax, of the microprocessor.
Furthermore, as microprocessors have become faster, operating voltages within the microprocessor core have decreased. This lower operating voltage makes it possible for circuitry within the microprocessor core to switch more rapidly. However, it also makes the circuitry more sensitive to small amounts of voltage noise.
Voltage noise can be somewhat mitigated by using bypass capacitors to decouple to power and ground pins on the microprocessor die. For example, FIG. 1 illustrates how a microprocessor die 102 is integrated into a conventional microprocessor system. As is illustrated in FIG. 1, microprocessor die 102 is electrically coupled to a package 104 through a number of microbumps (or solder balls) on the backside of die 102. Package 104 is also electrically coupled to circuit board 106 through larger solder balls on the backside of package 104.
Note that electrical signals from die 102 flow through vias in package 104 to conductors within circuit board 106. In particular, power and ground lines from die 102 flow through package 104 into circuit board 106. In additional to connecting to power and ground planes within circuit board 106, these power and ground lines also flow through vias in circuit board 106 and attach to bypass capacitors 108 on the backside of circuit board 106.
Note that the larger current loops, which flow from die 102 through package 104 and through circuit board 106 to bypass capacitors 108, cause a significant voltage droop due to loop inductance, L, that can cause increased noise at higher operating frequencies (i.e. signals with low dt). Note that loop inductance is due to the physical structure's metallic conductor dimensions, which must support current flow. Although the current flow does not cause inductance directly, changes in the current flow provide the di in the relation shipVvoltage—droop=L di/dt. 
To reduce inductance, some systems increase the size of the capacitance within the die itself to increase the dt term to acceptable levels for overall voltage droop. They also provide low inductance loops to board-level, or module-level decoupling. Unfortunately, providing capacitance within the die involves using gate oxide capacitors, which have leakage modes. This is highly undesirable because semiconductor technology is at the point where leakage current dominates power dissipation.
Hence, what is needed is a method and an apparatus for lowering loop inductance for bypass capacitors without the above-described problems.